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Download Design of Energy-Efficient Application-Specific Instruction by Tilman Glökler, Heinrich Meyr PDF

By Tilman Glökler, Heinrich Meyr

After a short creation to low-power VLSI layout, the layout area of ASIP guideline set architectures (ISAs) is brought with a distinct specialise in vital good points for electronic sign processing. in line with the levels of freedom provided by way of this layout house, a constant ASIP layout circulate is proposed: this layout move begins with a given software and makes use of incremental optimization of the ASIP undefined, of ASIP coprocessors and of the ASIP software program by utilizing a top-down strategy and by means of utilising application-specific alterations on all degrees of layout hierarchy. A vast variety of real-world sign processing purposes serves as motor vehicle to demonstrate each one layout determination and offers a hands-on method of ASIP layout. ultimately, whole case experiences reveal the feasibility and the potency of the proposed technique and quantitatively evaluation the advantages of ASIPs in an business context.

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Additional info for Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs)

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3) Ptotal = Istandby Vdd + Ileakage Vdd + Isc Vdd + αavg Cl Vdd = Pstandby + Pleakage + Pshort circuit + Pcapacitive The standby current Istandby is typically completely avoided by a proper CMOS circuit style and can usually be neglected. However for certain circuit styles (pseudo NMOS, NMOS pass transistor logic, and memory cores) Istandby can be an issue [197]. The leakage current Ileakage is due to the reverse bias current in the parasitic diodes of the diffusion zones and the bulk region of the MOS transistors and also due to the subthreshold current in the case of gate voltages below the threshold voltage.

Moreover, parameters like area efficiency for low data-rate tasks and flexibility requirements for errorprone and quickly changing control tasks have to be taken into account [91]. It is possible for some algorithms to use adaptive implementations, where the number of operations that are needed for this task can be scaled to reduce energy. g. ). However, if the application permits a certain algorithmic degradation under some circumstances, it might be advantageous to detect this condition and scale the algorithm accordingly.

Therefore, algorithmic transformations in order to reduce the number of memory accesses and/or to reduce the memory size are also effective power saving techniques on the system level (cf. [85], [181] and [42] for examples). Accesses to large memories should be reduced by using an appropriate memory hierarchy: starting with registers as the lowest level of hierarchy, this hierarchy ends with large on-chip or external memory banks. Accesses to registers are obviously much less power consuming (and typically also much faster) than accesses to larger memory blocks.

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